Carry save adder and carry look ahead adder using inverter chain based coplanar QCA full adder for low energy dissipation
نویسندگان
چکیده
منابع مشابه
Performance Analysis of 32-Bit Array Multiplier with a Carry Save Adder and with a Carry-Look-Ahead Adder
In this paper, design of two different array multipliers are presented, one by using carry-look-ahead (CLA) logic for addition of partial product terms and another by introducing Carry Save Adder (CSA) in partial product lines. The multipliers presented in this paper were all modeled using VHDL (Very High Speed Integration Hardware Description Language) for 32-bit unsigned data. The comparison ...
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In this paper focuses on carry -look ahead adders have done research on the design of high-speed, low-area, or low-power adders. Addition is the fundamental operation for any VLSI processors or digital signal processing. The main objective of this paper is to reduce the propagation delay and gate count of the Carry look-Ahead Adder (CLA).Which will also reflect in the reduction of area and powe...
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Abstract-Low-voltage and low-power circuit structures are substantive for almost all mobile electronic gadgets which generally have mixed mode circuit structures embedded with analog sub-sections. Using the reconfigurable logic of multiinput floating gate MOSFETs, 4-bit full adder has been designed for 1.8V operation. Multi-input floating gate (MIFG) transistors have been anticipating in realiz...
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We compare two 16 bit adders based on the Manchester Carry Chain (MCC) circuit topology using the TSMC .25 µm process technology. The first circuit is a synchronous 16 bit adder based on an optimized 4-bit MCC where the carry out of each of the 4-bit MCCs are ripple carried into the next MCC block through an edge sensitive D-Flip Flop. The second circuit is an asynchronous adder, which uses the...
متن کاملAn area-efficient static CMOS carry-select adder based on a compact carry look-ahead unit
This paper presents a highly area-efficient CMOS carry-select adder (CSA) with a regular and iterative-shared transistor structure very suitable for implementation in VLSI. This adder is based on both a static and compact multi-output carry look-ahead (CLA) circuit and a very simple select circuit. Comparisons with other representative 32-bit CSAs show that the proposed adder reduces the area b...
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ژورنال
عنوان ژورنال: Microelectronic Engineering
سال: 2019
ISSN: 0167-9317
DOI: 10.1016/j.mee.2019.03.015